1. Field of the Invention
The present invention relates to a test circuit and particularly to a test circuit for identification of locations of a circuit within an integrated circuit having low speed performance.
2. Description of the Prior Art
Integrated circuits (ICs) are cornerstones of myriad computational systems, such as personal computers and communications networks. Users of such systems have come to enjoy substantial and continual improvements in speed performance over time. The demand for speed encourages system designers to select ICs with superior speed performance. This leads IC manufacturers to carefully test the speed performance of their designs.
Integrated circuit devices typically include numerous electrical and/or electronic elements that are fabricated on, for example, silicon wafers to perform a particular function. The sequence of steps that occur in the course of manufacturing an IC device can be grouped broadly into design and fabrication phases.
The design phase begins by determining the desired functions and necessary operating specifications of the IC device. The IC device is then designed from the “top down”; that is, large functional blocks are first identified, then sub-blocks are selected, and the logic gates needed to implement the sub-blocks are chosen. Each logic gate is designed through the appropriate connection of, for example, transistors and resistors. The logic gates and other circuit components are then combined to form schematic diagrams.
After the various levels of design are completed, each level is checked to ensure correct functionality, and then test vectors are generated from the schematic diagrams. Next, the circuit is laid out. A layout consists of sets of patterns that will be transferred to the silicon wafer. These patterns correspond to, for example, the formation of transistors and interconnect structures. The layout is designed from the “bottom up”; for example, basic components (e.g., transistors) are first laid out, then logic gates are created by interconnecting appropriate basic components, forming the logic gates into sub-blocks, and finally connecting appropriate sub-blocks to form functional blocks. Power buses, clock-lines, and input-output pads required by the circuit design are also incorporated during the layout process. The completed layout is then subjected to a set of design rule checks and propagation delay simulations to verify that a correct implementation of the circuit design has been achieved. After this checking procedure, the layout is used to generate a set of masks to be used during the fabrication phase to specify the circuit patterns on the silicon wafer.
The fabrication phase that follows the design phase includes a sequence of process steps during which the set of masks transfer the layout patterns onto a silicon wafer using photolithographic and film formation processes. The process parameters (e.g., temperature, pressure, deposition rates and times, etch rates and times) associated with the process steps are typically developed and refined during an initial development stage. These refined process parameters are then used to produce a final fabrication process used during IC production.
Test structures formed on the wafer during the development stage of the fabrication phase are utilized to identify the precise structural nature of defects caused by non-optimal process parameters, thereby facilitating the refinement of the final fabrication process. These test structures are deemed necessary, as the physical nature of these defects cannot be discerned from output data of the ICs. Specifically, IC defects produce functional errors in the output data. These functional errors provide little or no information to identify the physical structure causing the defect. Even with test structures, information about the exact location and nature of the defect is still not readily obtainable. Thus, failure analysis remains difficult and time consuming.
Certain test structures are known in the prior art. For example, U.S. Pat. No. 5,790,479 discloses a test circuit for characterizing interconnect timing characteristics is disclosed in. Referring to FIG. 1, and as described in U.S. Pat. No. 5,790,479, a first inverter 110 has an output terminal 111 coupled to a first reference programmable intersection point (PIP) 114 by a first reference interconnect 112. The first reference PIP 114 is coupled to an input terminal 119 of a second inverter 120 by a second reference interconnect 116. A first test PIP 117 has a pass transistor which couples the second reference interconnect 116 to a first test interconnect 118 when the pass transistor of test PIP 117 is turned on. An output terminal 121 of the second inverter 120 is coupled to a second reference PIP 124 by a reference interconnect 122. The second reference PIP 124 is also coupled to an input terminal 129 of a third inverter 130 by a reference interconnect 126. A second test PIP 127 has a pass transistor which couples the reference interconnect 122 to a second test interconnect 128 when the pass transistor of the second test PIP 127 is turned on. An output terminal 131 of the third inverter 130 is coupled to a third reference PIP 134 by a reference interconnect 132. The third reference PIP 134 is also coupled to the input terminal of a buffer 140 by a reference interconnect 136. An output terminal 141 of the buffer 140 is coupled to a fourth reference PIP 144 by a reference interconnect 142. The fourth reference PIP 144 is also coupled to an input terminal 149 of a fourth inverter 150 by a reference interconnect 146.
An output terminal 151 of the fourth inverter 150 is coupled to a fifth reference PIP 154 by a reference interconnect 152. The fifth reference PIP 154 is coupled to the input terminal of a fifth inverter 160 by a reference interconnect 156. An output terminal 161 of the fifth inverter 160 is coupled to a sixth reference PIP 164 by a reference interconnect 162. The sixth reference PIP 164 is coupled to an input terminal 109 of the first inverter 110 by a reference interconnect 166. Each of the reference PIPs 114, 124, 134, 144, 154 and 164 has a pass transistor which is turned ON to allow current to flow through each of the six configuration logic blocks (CLBs) 110, 120, 130, 140, 150, and 160 forming the exemplary reference ring oscillator circuit (RROC) 100. In this state, if test PIPs 117, 127 are both turned OFF, the RROC 100 oscillates in an unloaded state. When at least one test PIP 117, 127 is turned ON, the RROC 100 is loaded by at least one test interconnect structure 118, 128 and the RROC 100 is said to be in a loaded state. Any one of the twelve reference interconnects 112, 116, 122, 126, 132, 136, 142, 146, 152, 156, 162, 166 may be coupled to a test interconnect structure by a test PIP. The test interconnect structures 118 and 128 can include an interconnect wire (e.g., single length line, longline, etc.) or any active device on the substrate of an integrated circuit.
Six segments of the RROC 100 are defined, each comprising a signal path which begins at a CLB output terminal 111, 121, 131, 141, 151, 161 of one stage and extends to a CLB input terminal 119, 129, 139, 149, 159 and 109, respectively, of the next stage in the ring. For example, a first segment of the RROC 100 begins at the CLB output terminal 111 of CLB 110 and ends at the CLB input terminal 119 of the next CLB 120. Test points, accessible to test probes (not shown), are provided at the input terminals 109, 119, 129, 139, 149 and 159, and at the output terminals 111, 121, 131, 141, 151 and 161 of each stage of the RROC 100. Segments of the RROC 100 having a test PIP are referred to as test segments of the RROC 100. Although there are only two test interconnect structures 118 and 128 shown in the RROC 100, every segment of the RROC 100 can be a test segment having a test PIP which couples a test interconnect structure to the segment.
FIG. 2 is a schematic diagram of an oscillator 200 including a pair of similar test circuits 210A and 210B, as disclosed in U.S. Pat. No. 6,134,191. Test circuits 210A and 210B may be any signal paths for which the associated signal propagation delays are applicable. For example, test circuits 210A and 210B are signal paths on a field-programmable gate array (FPGA).
Oscillator 200 provides a test-clock signal TCLK on a like-named output terminal. The period TTCLK of test-clock signal TCLK is a function of the propagation delay for rising-edge signals traversing test circuits 210A and 210B. The period TTCLK can therefore be used to determine the rising-edge delays DRA and DRB for respective test circuits 210A and 210B.
Test circuits 210A and 210B are included within a pair of respective signal paths 215A and 215B. Signal path 215A includes an output terminal 220 connected to the “0” input of a multiplexer 225; signal path 215B includes an output terminal 230 connected to the “1” input of multiplexer 225. Output terminal TCLK connects to respective input terminals of signal paths 215A and 215B and to the select input S of multiplexer 225. Also included in signal paths 215A and 215B are a respective pair of inverters 235A and 235B. Inverter 235A is connected between output terminal TCLK and an input terminal 240 of test circuit 210A. Inverter 220B is connected between an output terminal 245 of test circuit 210B and the “1” input of multiplexer 225.
However, the test circuits described in the patents identified above still suffer various shortcomings, such as each requires the test segments be tested one by one, which is time consuming.